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? semiconductor components industries, llc, 2009 august, 2009 ? rev. 4 1 publication order number: nb7l111m/d nb7l111m 2.5v / 3.3v, 6.125gb/s 1:10 differential clock/data driver with cml output description the nb7l111m is a low skew 1?to?10 differential clock/data driver, designed with clock/data distribution in mind. it accepts two clock/data sources into multiplexer input and reproduces ten identical cml differential outputs. this device is ideal for clock/data distribution across the backplane or a board, and redundant clock switchover applications. the input signals can be either differential or single?ended (if the external reference voltage is provided). differential inputs incorporate internal 50 termination resistors and accept negative ecl (necl), positive ecl (pecl), lvcmos, lvttl, cml, or lvds (using appropriate power supplies). the differential 16 ma cml output provides matching internal 50 termination, and 400 mv output swing when externally terminated 50 to v cc . the nb7l111m operates from a 2.5 v 5% supply or a 3.3 v 5% supply and is guaranteed over the full industrial temperature range of ? 40 c to +85 c. this device is packaged in a low profile 8x8 mm, qfn ? 52 package with 0.5 mm pitch (see package dimension on the back of the datasheet). application notes, models, and support documentation are available at www.onsemi.com. features ? maximum input clock frequency > 5.5 ghz typical ? maximum input data rate > 6.125 gb/s typical ? < 0.5 ps maximum clock rms jitter ? < 15 ps maximum data dependent jitter at 3.125 gb/s ? 50 ps typical rise and fall times ? 240 ps typical propagation delay ? 2 ps typical duty cycle skew ? 10 ps typical within device skew ? 15 ps typical device ? to ? device skew ? operating range: v cc = 2.5 v 5 and 3.3 v 5 ? 400 mv differential cml output swing ? 50 internal input and output termination resistors ? pb ? free packages are available* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. a = assembly site wl = wafer lot yy = year ww = work week g = pb ? free package *for additional marking information, refer to application note and8002/d. qfn ? 52 mn suffix case 485m marking diagram* http://onsemi.com http://onsemi.com see detailed ordering and shipping information in the package dimensions section on p age 12 of this data sheet. ordering information 152 nb7l 111m awlyywwg 1 52
nb7l111m http://onsemi.com 2 nc q0 q0 v ee q1 q1 v ee v cc q2 v ee v cc q3 q2 nc v ee vtclk0 sel q4 v ee v cc nc q8 q7 v ee q7 q9 1 2 3 4 5 6 7 8 9 10 11 12 13 clk0 clk0 vtclk0 vtsel sel vtsel vtclk1 clk1 clk1 vtclk1 14 15 16 17 18 19 20 21 22 23 24 25 26 v cc q9 v ee q8 v cc nc v ee 39 38 37 36 35 34 33 32 31 30 29 28 27 q4 v ee q3 52 51 50 49 48 47 46 45 44 43 42 41 40 v cc exposed pad (ep) qfn52 q5 q5 v ee q6 q6 figure 1. pinout (top view) clk0 clk0 clk1 clk1 sel q 0 q 0 q 1 q 1 q 2 q 2 q 3 q 3 q 4 q 4 q 5 q 5 q 6 q 6 q 7 q 7 q 8 q 8 q 9 q 9 vtclk0 vtclk1 vtclk1 vtsel figure 2. logic diagram 50 r 2 r 3 50 vtclk0 50 50 50 50 sel vtsel r 1 v cc v ee 0 1 table 1. function table sel sel clk0/clk0 clk1/clk1 low high on off high low off on
nb7l111m http://onsemi.com 3 table 2. pin description pin name i/o description 15, 24, 27, 39, 42, 51 v cc ? positive supply voltage. all v cc pins must be externally connected to power supply to guarantee proper operation. 1, 18, 21, 26, 30, 33, 36, 40, 45, 48 v ee ? negative supply voltage. all v ee pins must be externally connected to power supply to guarantee proper operation. 2 vtclk0 ? internal 50 termination pin for clk0. (note 2) 3 clk0 lvpecl, cml, lvcmos, lvttl, lvds input non ? inverted differential clock/data input 0 (note 2). 4 clk0 lvpecl, cml, lvcmos, lvttl, lvds input inverted differential clock/data input 0 (note 2). 5 vtclk0 ? internal 50 termination pin for clk0 . (note 2) 6 vtsel internal 50 termination pin for sel. (note 2) 7 sel lvpecl, cml, lvcmos, lvttl, lvds input non ? inverted differential clock/data select input. internal 75 k to v ee . 8 sel lvpecl, cml, lvcmos, lvttl, lvds input inverted differential clock/data select input. internal 56 k to v cc and 56 k to v ee bias this pin to (v cc ? v ee )/2. 9 vtsel lvpecl, cml, lvcmos, lvttl, lvds input internal 50 termination pin for sel . (note 2) 10 vtclk1 ? internal 50 termination pin for clk1. (note 2) 11 clk1 lvpecl, cml, lvcmos, lvttl, lvds input non ? inverted differential clock/data input 1 (note 2). 12 clk1 lvpecl, cml, lvcmos, lvttl, lvds input inverted differential clock/data input 1 (note 2). 13 vtclk1 ? internal 50 termination pin for clk1 . (note 2) 14, 25, 41, 52 nc ? 17, 20, 23, 29, 32, 35, 38, 44, 47, 50 q[0 ? 9] cml outputs non ? inverted cml outputs [0 ? 9] with internal 50 source termination resistor (note 1). 16, 19, 22, 28, 31, 34, 37, 43, 46, 49 q[0 ? 9] cml outputs inverted cml outputs [0 ? 9] with internal 50 source termination resistor (note 1). ep ? ? exposed pad (ep). the thermally exposed pad on package bottom (see case drawing) must be attached to a heat ? sinking conduit on the printed circuit board. 1. cml output requires 50 receiver termination resistor to v cc for proper operation. 2. in the dif ferential configuration when the input termination pin (vtclk, vtclk ) are connected to a common termination voltage or left open, and if no signal is applied on clk and clk then the device will be susceptible to self ? oscillation.
nb7l111m http://onsemi.com 4 table 3. attributes characteristics value input default state resistors r1, r3 r2 56 k 75 k esd protection human body model machine model > 1400 v > 80 v moisture sensitivity (note 3) pb pkg pb ? free pkg qfn ? 52 level 2 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 339 meets or exceeds jedec spec eia/jesd78 ic latchup test 3. for additional information, see application note and8003/d. table 4. maximum ratings (note 4) symbol parameter condition 1 condition 2 rating unit v cc positive power supply v ee = 0 v 3.6 v v i input voltage v ee = 0 v v ee v i v cc 3.6 v v inpp differential input voltage |clk ? clk | v cc ? v ee 2.8 v v cc ? v ee < 2.8 v 2.8 |v cc ? v ee | v v i in input current through r t (50 resistor) continuous surge 25 50 ma ma i out output current continuous surge 25 50 ma ma t a operating temperature range qfn52 ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 5) 0 lfpm 500 lfpm qfn52 25 19.6 c/w c/w jc thermal resistance (junction ? to ? case) 1s2p (note 8) qfn52 21 c/w t sol wave solder pb pb ? free 265 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 4. maximum ratings are those values beyond which device damage may occur. 5. jedec standard multilayer board ? 1s2p (1 signal, 2 power).
nb7l111m http://onsemi.com 5 table 5. dc characteristics v cc = 2.375 v 2.625 v and 3.135 v to 3.465 v, v ee = 0 v, t a = ? 40 c to +85 c (notes 6 and 7) symbol characteristic min typ max unit i cc power supply current (inputs and outputs open) v cc = 2.375 v to 2.625 v v cc = 3.135 v to 3.465 v 255 270 290 305 325 340 ma v oh output high voltage (notes 6 and 7) v cc ? 40 v cc ? 20 v cc mv v ol output low voltage (notes 6 and 7) v cc = 2.375 v to 2.625 v v cc = 3.135 v to 3.465 v v cc ? 440 v cc ? 490 v cc ? 350 v cc ? 400 v cc ? 290 v cc ? 340 mv differential input driven single ? ended (see figures 13 and 15) v th input threshold reference voltage range (note 8) 1125 v cc ? 75 mv v ih single ? ended input high voltage (note 7) v th + 75 v cc mv v il single ? ended input low voltage (note 7) v ee v cc ? 150 mv differential inputs driven differentially (see figures 14 and 16) v ihd differential input high voltage 1200 v cc mv v ild differential input low voltage v ee v cc ? 75 mv v cmr input common mode range (differential configuration) (note 9) 1163 v cc ? 37 mv v id differential input voltage (v ihd ? v ild ) 75 2500 mv i ih input high current clk[0 ? 1]/clk[0 ? 1] (termination pins open) sel/sel ? 100 ? 150 5 100 150 a i il input low current clk[0 ? 1]/clk[0 ? 1] (termination pins open) sel/sel ? 100 ? 150 5 100 150 a r tin internal input termination resistor 45 50 55 r tout internal output termination resistor 45 50 55 r te m p coef internal i/o termination resistor temperature coefficient ? 3.75 m /c note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. cml outputs require 50 receiver termination resistors to v cc for proper operation. 7. input and output parameters vary 1:1 with v cc . 8. v th is applied to the complementary input when operating in single ? ended mode. 9. v cmr (min) varies 1:1 with v ee , v cmr (max) varies 1:1 with v cc .
nb7l111m http://onsemi.com 6 table 6. ac characteristics v cc = 2.375 v to 2.625 v and 3.135 v to 3.465 v, v ee = 0 v; (note 10) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max v outpp output voltage amplitude (@ v inppmin ) (see figures 3, 4, 5, and 6) v cc = 2.375 v to 2.625 v f in 3 ghz f in 5.5 ghz v cc = 3.135 v to 3.465 v f in 3 ghz f in 5.5 ghz 240 115 250 130 330 220 350 250 240 115 250 130 330 220 350 250 240 115 250 130 330 220 350 250 mv f data maximum operating data rate 5 6 5 6 5 6 gb/s t plh , t phl differential input ? to ? output propagation delay @ 1 ghz (see figures 7 and 11) clk ? q sel ? q 200 290 240 340 280 390 200 290 240 340 280 390 200 290 240 340 280 390 ps t skew duty cycle skew (note 11) within device skew device ? to ? device skew (note 15) 2 10 15 15 20 80 2 10 15 15 20 80 2 10 15 15 20 80 ps t jitter rms random clock jitter (note 13) f in = 3 ghz f in = 5.5 ghz peak ? to ? peak data dependent jitter (note 14) f data = 3.125 gb/s f data = 5 gb/s f data = 6.125 gb/s 0.2 0.2 6 15 15 0.5 0.5 15 25 25 0.2 0.2 6 15 15 0.5 0.5 15 25 25 0.2 0.2 6 15 15 0.5 0.5 15 25 25 ps v inpp input voltage swing/sensitivity (differential configuration) (note 12 and figures 3, 4, 5, and 6) 75 400 2500 75 400 2500 75 400 2500 mv t r t f output rise/fall times @ 1 ghz (20% ? 80%) 50 75 50 75 50 75 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. measured by forcing v inpp (min) from a 50% duty cycle clock source. all loading with an external r l = 50 to v cc . input edge rates 40 ps (20% ? 80%). 11. duty cycle skew is measured between differential outputs using the deviations of the sum of tpw ? and tpw+ @ 1 ghz. 12. v inpp (max) cannot exceed v cc ? v ee . input voltage swing is a single ? ended measurement operating in differential mode. 13. additive rms jitter with 50% duty cycle clock signal. 14. additive peak ? to ? peak data dependent jitter with input nrz data at prbs 2 23 ? 1. 15. device ? to ? device skew is measured between outputs under identical transition and conditions @ 1 ghz.
nb7l111m http://onsemi.com 7 0 50 100 150 200 250 300 350 400 1 2 3 3.5 4 4.5 5 5.5 6 6.5 output voltage amplitude ( m v) input clock frequency (ghz) 25 85 ? 40 figure 3. output voltage amplitude vs. input clock frequency and temperature (v inpp = 400 mv; v cc = 3.3 v) 0 50 100 150 200 250 300 350 400 1 2 3 3.5 4 4.5 5 5.5 6 6.5 output voltage amplitude (mv) input clock frequency (ghz) figure 4. output voltage amplitude vs. input clock frequency and temperature (v inpp = 75 mv; v cc = 3.3 v) 25 85 ? 40 0 50 100 150 200 250 300 350 400 1 2 3 3.5 4 4.5 5 5.5 6 6.5 0 50 100 150 200 250 300 350 400 1 2 3 3.5 4 4.5 5 5.5 6 6.5 input clock frequency (ghz) output voltage amplitude (mv) ? 40 85 25 output voltage amplitude (mv) input clock frequency (ghz) 25 85 ? 40 figure 5. output voltage amplitude vs. input clock frequency and temperature (v inpp = 400 mv; v cc = 2.5 v) figure 6. output voltage amplitude vs. input clock frequency and temperature (v inpp = 75 mv; v cc = 2.5 v) figure 7. propagation delay versus temperature ? 40 25 85 200 210 220 230 240 250 260 270 280 temperature ( c) propagation delay (ps) typical tpd
nb7l111m http://onsemi.com 8 figure 8. typical output waveform at 3.125 gb/s with prbs 2 23 ? 1 (v inpp = 75 mv ? left and 400 mv ? right) device ddj = 6 ps device ddj = 7 ps voltage (50 mv/div) time (22.1 ps/div) voltage (50 mv/div) time (22.1 ps/div) figure 9. typical output waveform at 5 gb/s with prbs 2 23 ? 1 (v inpp =75 mv ? left and 400 mv ? right) device ddj=16ps device ddj=17ps voltage (40 mv/ div) time (22.1 ps/div) voltage (40 mv/ div) time (22.1 ps/div) figure 10. typical output waveform at 6.125 gb/s with prbs 2 23 ? 1 (v inpp = 75 mv ? left and 400 mv ? right) device ddj=12ps device ddj=15ps voltage (35 mv/div) time (22.1 ps/div) voltage (35 mv/div) time (22.1 ps/div)
nb7l111m http://onsemi.com 9 figure 11. ac reference measurement clk clk q q t phl t plh v inpp = v ih (clk) ? v il (clk) v outpp = v oh (q) ? v ol (q) receiver device q clk 50 50 figure 12. typical termination for 16 ma output drive and device evaluation q clk v cc 50 50 v cc nb7l111m clk v th clk v th figure 13. differential input driven single ? ended clk clk figure 14. differential inputs driven differentially v ihmax v ilmax v ih v th v il v ihmin v ilmin v cc v thmax v thmin gnd v th v ihdmax v ildmax v ihdmin v ildmin v ihdtyp v ildtyp v id = v ihd ? v ild v cmr v cc v cmmax v cmmax gnd figure 15. v th diagram figure 16. v cmr diagram
nb7l111m http://onsemi.com 10 q q v cc 16 ma 50 50 figure 17. cml output structure v ee table 7. interfacing options interfacing options connections cml connect vtclk0, vtclk0 , vtclk1, vtclk1 , vtsel, vtsel to v cc lvds connect vtclk0, vtclk0 together for clk0 input; connect vtclk1, vtclk1 together for clk1 input; connect vtsel, vtsel together for sel control input. ac ? coupled bias vtclk0, vtclk0 , vtsel, vtsel and vtclk1, vtclk1 inputs within (vcmr) common mode range. rsecl, lvpecl standard ecl termination techniques. see and8020. lvttl, lvcmos an external voltage should be applied to the unused complementary differential input. nominal voltage 1.5 v for lvttl and v cc /2 for lvcmos inputs.
nb7l111m http://onsemi.com 11 application information all nb7l111m inputs can accept lvpecl, cml, lvttl, l vcmos and lvds signal levels. the limitations for differential input signal (lvds, pecl, or cml) are minimum input swing of 75 mv pp and the maximum input swing of 2500 mv pp . within these differential conditions, the input high voltage can range from v cc to 1.2 v. examples of interfaces are illustrated below in a 50 environment (z = 50 ). 50 v cc clk clk 50 cml or nb7l111m v cc v tclk v ee v cc q 50 50 cml or nb7l111m v ee figure 18. cml to cml interface q 50 v cc v cc lvds driver 50 nb7l111m v ee v ee figure 19. pecl to cml receiver interface 50 v cc v cc pecl driver clk clk 50 nb7l111m v ee v tclk v ee r t r t v ee v cc r t 5.0 v 290 3.3 v 150 2.5 v 80 recommended r t values v cc v tclk v bias * v tclk clk clk v tclk v tclk figure 20. lvds to cml receiver interface *v bias is within v cmr range. z o = 50 z o = 50 z o = 50 z o = 50 z o = 50 z o = 50
nb7l111m http://onsemi.com 12 figure 21. lvcmos/lvttl to cml receiver interface 50 v cc v cc lvttl/ lvcmos driver clk clk 50 nb7l111m v ee no connect v tclk v cc v tclk no connect v ref v ref lvcmos lvttl 1.5 v recommended v ref values v cc v ee 2 z o = 50 ordering information device package shipping ? NB7L111MMN qfn ? 52 260 units / tray NB7L111MMNg qfn ? 52 (pb ? free) 260 units / tray NB7L111MMNr2 qfn ? 52 2000 / tape & reel NB7L111MMNr2g qfn ? 52 (pb ? free) 2000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nb7l111m http://onsemi.com 13 package dimensions case 485m ? 01 issue b c 0.15 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. a d e b c 0.08 a1 a3 a d2 l note 3 c 0.15 2x 2x seating plane c 0.10 a2 c e2 52 x e 1 13 14 26 27 39 40 52 b 52 x a 0.10 b c 0.05 c dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a2 0.60 0.80 a3 0.20 ref b 0.18 0.30 d 8.00 bsc d2 6.50 6.80 e 8.00 bsc e2 6.50 6.80 e 0.50 bsc k 0.20 --- ref k 52 x l 0.30 0.50 pin one reference on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 nb7l111m/d the products described herein (nb7l111m), may be covered by u.s. patents including 6,362,644 . there may be other patents pending. gigacomm is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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